A Hardware Architecture for a Parallel Genetic Algorithm for Image Registration

Introduction Parallel Genetic Algorithms (PGAs) have frequently been cited as an important area of research as they provide a means of rapidly developing a solution to a wide range of problems. Real-time image analysis is one of the areas of research which would particularly benefit from PGAs, however such algorithms are generally simulated on conventional computers or are designed for expensive hardware systems. For practical image processing on a large scale, cheap, fast and efficient PGA processors are required as part of a vision system. Vision systems require processing techniques which are robust, fast and capable of dealing with large quantities of data. Genetic algorithms have been used because of the first of these criteria, as is exemplified in the works of Fitzpatrick 1984, Mandava 1989, McAulay 1989. However by using hardware parallel genetic algorithms the second and third criteria could also be fulfilled. Fitzpatrick suggests that a parallel implementation would be beneficial and various forms of Parallel Genetic Algorithm (PGA) have been suggested by other authors. Many of the different techniques are covered in the five international conference proceedings on genetic algorithms and the first Workshop on Parallel Problem Solving from Nature. In this paper the nature of Parallel Genetic Algorithms is described followed by the application of genetic algorithms to vision systems. A description of a hardware architecture for vision systems is detailed along with various modifications to improve the implementation. A simulation is used to produce results that verify the effectiveness of the hardware architecture and finally conclusions and future work are discussed.